1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a Multi-Chip Package (MCP) type semiconductor memory device including a plurality of memory chips and one memory controller chip which are provided in one package.
2. Description of the Related Art
In the field of mobile devices such as mobile phones, advanced functions, such as functions to store and reproduce still images, moving images, and music, and a game function, have been increasingly adopted and there has also been a great demand for high speed processing of a large amount of data. Thus, there is a need to increase storage capacity while achieving a reduction in the size of the semiconductor memory. MCP, which incorporates a plurality of memory chips into one package, is a package technology developed to meet such a need. Particularly, a stack MCP including a stack of two or more chips is effective in reducing package size.
If one defective cell is present in a memory chip provided in the MCP type semiconductor memory, the entire semiconductor memory becomes defective even when other memory chips are not defective, causing great loss. To remedy defective cells present in each memory chip, the MCP type semiconductor memory is provided with a reserve storage region (including redundant cells) separately from a conventional storage region so as to replace detective cells with redundant cells. A fuse circuit is generally used as a means for replacing defective cells with redundant cells.
Meanwhile, Japanese Patent Kokai No. 2005-135183 (Patent Literature 1) describes an MCP type memory system including one nonvolatile memory LSI and a plurality of volatile memories LSI. The nonvolatile memory LSI of this memory system includes a command issuance circuit that issues a command to perform defect remedy (or defect compensation) of the volatile memory LSI. The volatile memory LSI includes a decoder circuit that decodes a command sent from the command issuance circuit and a volatile defect information holding circuit that holds defect remedy information. Defect remedy of the volatile memory LSI is performed based on the defect remedy information held by the defect information holding circuit.
For the memory system described in the patent Literature 1 described above, it is necessary to design two types of memory chips, the nonvolatile memory LSI and the volatile memory LSI, requiring a significant development time. Even when memory elements are constructed of, for example, only nonvolatile memories, there is a need to provide a memory chip including a circuit for generating a command to perform defect remedy and a memory chip including a circuit for decoding the command. That is, in this case, it is also necessary to design two types of memory chips for a single product and it is difficult to reduce the number of development processes and manufacturing costs. Another solution may be considered in which both a command generator and a command decoder are formed in one memory chip and one of the generator and decoder functions is selected upon packaging. However, this is undesirable since an unused function remains in the chip, causing an increase in chip area.